1. Field of the Invention
The present invention relates to a liquid crystal display panel having a horizontal electric field. More particularly, the present invention relates to a liquid crystal display panel and a method of fabricating the same that improve an aperture ratio.
2. Description of the Related Art
In general, a liquid crystal display (LCD) device controls light transmittance of liquid crystal material using an electric field to display a picture. The liquid crystal display device is classified into a vertical electric field type and a horizontal electric field type based upon a direction of the electric field driving the liquid crystal.
The liquid crystal display device of the vertical electric field type, in which a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate are arranged to face each other, drives a liquid crystal of a twisted nematic (TN) mode using a vertical electric field formed between the common electrode and the pixel electrode. The liquid crystal display device of the vertical electric field type has an advantage of a large aperture ratio; however, it has a defect of a narrow viewing angle of about 90°.
The liquid crystal display device of the horizontal electric field type drives a liquid crystal of an in-plane switch (hereinafter referred to as “IPS”) mode using a horizontal electric field between the pixel electrode and the common electrode parallel on the lower substrate. The liquid crystal display device of the horizontal electric field type has an advantage of a wide viewing angle of about 160°. Hereinafter, the liquid crystal display device of horizontal electric field type will be described in detail.
The liquid crystal display device of the horizontal electric field type includes a thin film transistor array substrate (a lower substrate) and a color filter array substrate (an upper substrate) that face and are joined to each other, a spacer for uniformly maintaining a cell gap between the two substrates and a liquid crystal injected into a space provided by the spacer.
The thin film transistor array substrate includes a plurality of signal lines for forming a horizontal electric field on a basis of a pixel, a plurality of thin film transistors, and an alignment film applied for a liquid crystal alignment thereon. The color filter array substrate includes a color filter for representing a color, a black matrix for preventing light leakage and an alignment film applied for a liquid crystal alignment thereon.
FIG. 1 is a plan view illustrating a part of a related art thin film transistor substrate of a horizontal electric field type, and FIG. 2 is a sectional view of the thin film transistor array substrate taken along the line I-I′ in FIG. 1.
In FIGS. 1 and 2, the related art thin film transistor array substrate of the horizontal electric field type includes a gate line 2 and a data line 4 formed on a lower substrate 45 crossing each other, a thin film transistor 6 formed at each crossing, a pixel electrode 14 and a common electrode 18 formed in order to apply the horizontal electric field in pixel regions defined by the crossing and a common line 16 connected to the common electrode 18. Moreover, the related art thin film transistor array substrate further comprises a storage capacitor 20 formed an overlapped portion between the pixel electrode 14 and the common line 16.
The gate line 2 supplies a gate signal to the gate electrode 8 of the thin film transistor 6. The data line 4 supplies a pixel signal to the pixel electrode 14 via a drain electrode 12 of the thin film transistor 6. The gate line 2 and the data line 4 are formed in a crossing arrangement to define the pixel region 5.
The common line 16 is formed parallel to the gate line 2 and supplies a reference voltage for driving the liquid crystal to the common electrode 18.
The thin film transistor 6 responds to the gate signal of the gate line 2 so that the pixel signal of the data line 4 is charged to the pixel electrode 14. To this end, the thin film transistor 6 comprises a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4 and a drain electrode 12 connected to the pixel electrode 14. Further, the thin film transistor 6 includes an active layer 15 overlapping the gate electrode 8 with a gate insulating film 46 positioned between the thin film transistor 6 and the gate electrode 8 and defining a channel between the source electrode 10 and the drain electrode 12. On the active layer 15, an ohmic contact layer 48 for making an ohmic contact with the source electrode 10 and the drain electrode 12 is further formed.
The pixel electrode 14, which is connected to a storage electrode 22 connected the drain electrode 12 of the thin film transistor 6 via a first contact hole 13 passing through a passivation film 34, is formed in the pixel region 5. The pixel electrode 14 comprises a first horizontal part 14A formed in parallel with the gate line 2 and a second horizontal part 14B formed to overlap the common line 16 and a finger part 14C formed parallel to the common electrode 18 between the first horizontal part 14A and the second horizontal part 14B.
The common electrode 18 is connected to the common line 16 and is formed in the pixel region 5. In addition, the common electrode 18 is formed parallel to the finger part 14C of the pixel electrode 14 in the pixel region 5.
Accordingly, a horizontal electric field is formed between the pixel electrode 14, to which the pixel signal is supplied via the thin film transistor 6, and the common electrode 18, to which the reference voltage is supplied via the common line 16. Moreover, the horizontal electric field is formed between the finger part 14C of the pixel electrode 14 and the common electrode 18. The liquid crystal molecules arranged in a horizontal direction between the thin film transistor array substrate and the color filter array substrate rotate due to a dielectric anisotropy. The light transmittance transmitting the pixel region 5 differs in accordance with a rotation amount of the liquid crystal molecules and thereby the pictures can be represented.
The storage capacitor 20 is connected to the common electrode 18, the storage electrode 22 overlapping the common electrode 18 with the gate insulating film 46, and a pixel electrode 14 via a second contact hole 21 passing through the storage electrode 22 and the passivation film 34. The storage capacitor 20 allows a pixel signal charged in the pixel electrode 14 to be maintained until the next pixel signal is charged.
FIGS. 3A to 3E are sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate shown in FIG. 2.
A gate metal layer is deposited on the lower substrate 45 by a deposition technique such as sputtering. Then, the gate metal layer is patterned by photolithography and an etching process using a mask. A gate pattern including the gate line 2, the gate electrode 8, the common line 16 and common electrode 18 are formed. Herein, a gate metal is formed with a mono layer or a double layer of chrome (Cr), molybdenum (Mo) or an aluminum or aluminum alloy metal.
In FIG. 3B, a gate insulating film 46 is formed on the lower substrate 45 provided with the gate pattern. The gate insulating film 46 is made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).
On the lower substrate 45 provided with the gate insulating film 46, an amorphous silicon layer, a n+ amorphous silicon layer are sequentially provided by deposition techniques such as the plasma enhanced chemical vapor deposition (PECVD) and the sputtering.
The amorphous silicon layer and the n+ amorphous silicon layer are patterned by a photolithography process and an etching process using a mask. Accordingly, the active layer 15 and the ohmic contact layer 48 are formed as shown in FIG. 3B.
On the lower substrate 45 provided with the active layer 15 and the ohmic contact layer 48, a source/drain metal layer is entirely formed by deposition techniques such as the plasma enhanced chemical vapor deposition (PECVD) and the sputtering, etc.
On the source/drain metal layer, a photo-resist pattern is formed by a photolithography process using a mask.
Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern. Accordingly, the source/drain patterns including the data line 4, the source electrode 10, the drain electrode 12 and the storage electrode 22 are formed.
Next, the ohmic contact layer 48 of a channel portion is etched using the source electrode 10 and the drain electrode 12 as a mask to thereby expose the active layer of the channel portion.
Herein, the source/drain metal layer is made of molybdenum (Mo), titanium (Ti), tantalum (Ta) or molybdenum alloy.
On the lower substrate 45 provided with the source/drain patterns, a passivation film 34 is entirely formed by deposition techniques such as a plasma enhanced chemical vapor deposition (PECVD) and a sputtering. The passivation film 34 is then patterned by the photolithography process and the etching process using a mask. Accordingly, a first and a second contact holes 13 and 21 are formed as shown in FIG. 3D. The first contact hole 13 is formed in such a manner as to pass through the passivation film 34 and expose the drain electrode 12, whereas the second contact hole 21 is formed in such a manner to pass through the passivation film 34 and exposes the storage electrode 22. Herein, the passivation film 34 is made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).
On the lower substrate 45 provided with the passivation film 34, a transparent electrode material is deposited by a deposition technique such as sputtering. The transparent electrode material is then patterned by photolithography and the etching process using a mask. Accordingly, the pixel electrode 14 is formed as shown in FIG. 3E. The pixel electrode 14 is electrically connected, via the first contact hole 13, to the drain electrode 12 and is electrically connected, via the second contact hole 21, to the storage electrode 22. The transparent electrode material may be indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO).
As described above, the related art thin film transistor array substrate of a horizontal electric field type liquid crystal display device has a problem that an aperture ratio is reduced in accordance with areas of the common electrode 18 and the common line 16 at the pixel region 5.